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rej03f0001-0600 rev.6.00 jul 01, 2008 page 1 of 29 ha16163t synchronous phase shift full-bridge control ic rej03f0001-0600 rev.6.00 jul 01, 2008 features ? high frequency operation; oscillator frequency = 2 mhz max. ? full-bridge phase-shift switching circuit with adjustable delay times ? integrated secondary synchronous rectifica tion control with adjustable delay times ? three-level over current protection; pulse by pulse, timer latch, one shot ocp ? package: tssop-20 application ? 48 v input isolated dc/dc converter ? primary; full-bridge circuit topology ? secondary; current doubler or center-tapped rectification illustrative circuit gnd rt sync ss remote delay -1 delay -2 delay -3 vref vcc vbias out -a out -b cs ramp out -c out -d out -f out -e fet driver fet driver fet driver fet driver fet driver optical feedback circuitry +48v + ? fb comp fet driver
ha16163t rej03f0001-0600 rev.6.00 jul 01, 2008 page 2 of 29 pin arrangement (top view) 2 3 4 5 6 7 8 rt gnd out-a out-b out-c out-d out-e out-f vcc vref 20 19 18 17 16 15 14 13 9 12 11 1 sync ramp cs comp remote fb ss delay-1 delay-2 10 delay-3 pin functions pin no. pin name pin function 1 sync synchronization i/o for the oscillator 2 ramp current sense signal input for the full-bridge control loop 3 cs current sense signal input for ocp 4 comp error amplifier output 5 remote remote on/off control 6 fb voltage feedback input 7 ss timing capacitor for both soft start and timer latch 8 delay-1 delay time adjustor for the full-bridge control signal (out-a and b) 9 delay-2 delay time adjustor for the full-bridge control signal (out-c and d) 10 delay-3 delay time adjustor for the secondary control signal (out-e and f) 11 vref 5 v/20 ma output 12 vcc ic power supply input 13 out-f secondary control signal 14 out-e secondary control signal 15 out-d full-bridge control signal 16 out-c full-bridge control signal 17 out-b full-bridge control signal 18 out-a full-bridge control signal 19 gnd ground level for the ic 20 rt timing resistor for the oscillator
ha16163t rej03f0001-0600 rev.6.00 jul 01, 2008 page 3 of 29 block diagram ? ? ? ? uvl l uvlo h l h vref good vref out-a out-b delay-1 vref 4v clamp circuit 500 ? ? lockout limit in s r q vref good vref good circuit bias zero delay s r q s r q discharge fault logic one pulse seq. vref vref delay delay out-c out-d delay-2 vref vref delay delay out-e out-f delay-3 vref vref delay delay zero delay
ha16163t rej03f0001-0600 rev.6.00 jul 01, 2008 page 4 of 29 absolute maximum ratings (ta = 25c) item symbol rating unit note power supply voltage vcc 20 v 1 peak output current ipk-out 50 ma 2, 3 dc output current idc-out 5 ma 3 vref output current iref-out ?20 ma 3 comp sink current isink-comp 2 ma 3 delay set current iset-delay 0.3 ma 3 rt set current iset-rt 0.3 ma 3 vref terminal voltage vter-ref ?0.3 to 6 v 1, 4 terminal group 1 voltage vter-1 ?0.3 to (vref +0.3) v 1, 5 operating junction temperatur e tj-opr ?40 to +125 c 6 storage temperature tstg ?55 to +150 c notes: 1. rated voltages are wi th reference to the gnd pin. 2. shows the transient current when driving a capacitive load. 3. for rated currents, inflow to the ic is indicated by (+), and outflow by (?). 4. vref pin voltage must not exceed vcc pin voltage. 5. terminal group 1 is defined the pins; remote, cs, ramp, comp, fb, ss, rt, sync, delay-1 to 3, out-a to f 6. ja 228c/w board condition; glass epoxy 55 mm 45 mm 1.6 mm, 10% wiring density.
ha16163t rej03f0001-0600 rev.6.00 jul 01, 2008 page 5 of 29 electrical characteristics (ta = 25c, vcc = 12 v, rt = 33 k , rdelay = 51 k , unless otherwise specified.) item symbol min typ max unit test conditions start threshold vh 9.0 9.8 10.6 v shutdown threshold vl 7.3 7.9 8.5 v uvlo hysteresis dv uvl 1.7 1.9 2.1 v start-up current is ? 90 150 a vcc = 8.5v supply operating current icc ? 7 10 ma no load on vref pin output voltage vref 4.9 5.0 5.1 v line regulation vref-line ? 0 10 mv vcc = 10v to 16v load regulation vref-load ? 6 20 mv iref = ?1ma to ?20ma vref temperature stability dvref/dta ? 80 * 1 ? ppm/c ta = ?40 to 105c oscillator frequency fosc ? 960 * 1 ? khz switching frequency fsw 412 480 547 khz measured on out-a, -b line stability fsw-line ?1.5 0 1.5 % vcc = 10v to 16v temperature stability dfsw/dta ? 0.1 * 1 ? %/c ta = ?40 to 105c oscillator rt voltage v rt 2.5 2.7 2.9 v input threshold v th-sync 2.5 2.85 3.2 v output high v oh-sync 3.5 4.0 ? v r sync = 33k to gnd output low v ol-sync ? 0.05 0.15 v r sync = 33k to vref minimum input pulse t i-min 50 ? ? ns sync output pulse width t o-sync ? 500 ? ns on threshold voltage v on 1.374 1.417 1.460 v off threshold voltage v off 1.293 1.333 1.373 v remote input bias current i remote 0 0.4 2 a remote = 2v fb input voltage v fb 1.225 1.250 1.275 v fb and comp are shorted fb input current i fb ?1.0 0 1.0 a fb = 1.25v open-loop dc gain av ? 80 * 1 ? db unity gain bandwidth bw ? 2 * 1 ? mhz output source current i source ?610 ?430 ?350 a fb = 0.75v, comp = 2v output sink current i sink 2.0 6.5 ? ma fb = 1.75v, comp = 2v output high voltage v oh-eo 3.7 3.9 ? v fb = 0.75v, comp; open output low voltage v ol-eo ? 0.1 0.4 v fb = 1.75v, comp; open error amplifier output clamp voltage * 2 v clamp-eo ?0.16 ?0.07 0.0 v fb = 0.75v, comp; open ss = 1v notes: 1. reference values for design. not 100% tested in production. 2. v clamp-eo = v comp ? ss voltage (1v)
ha16163t rej03f0001-0600 rev.6.00 jul 01, 2008 page 6 of 29 electrical characteristics (cont.) (ta = 25c, vcc = 12 v, rt = 33 k , rdelay = 51 k , unless otherwise specified.) item symbol min typ max unit test conditions ramp offset voltage v ramp ? 0.4 * 1 ? v ramp bias current i ramp ?5 ?0.8 5 a ramp = 0.3v ramp sink current i sink-ramp 8 26 ? ma ramp = 1v, comp = 0v minimum phase shift dmin ? 0 * 1 * 4 ? % ramp = 1v, comp = 0v maximum phase shift dmax ? 97.0 * 1 * 4 ? % ramp = 0v, comp = 2.1v phase modulator delay to out-c, -d * 2 tpd ? 30 60 ns comp = 2.1v delay-1, -2, -3 * 3 t d1, 2, 3 22 33.5 45 ns delay set r = 51k delay terminal voltage v d1, 2, 3 1.9 2.0 2.1 v delay set r = 51k source current i ss ?14 ?10 ?6 a ss = 1v discharge current i res-ss 5 10 ? ma ss = 1v, remote = 0v soft-start reset voltage v res-ss 0.25 0.40 0.55 v measured on ss soft start ss high voltage v oh-ss 3.9 4.0 4.1 v notes: 1. reference values for design. not 100% tested in production. 2. tpd is defined as; ramp 1v 50% 50% tpd 0v 5v 0v out-c/d 3. t d1, 2, 3 are defined as; t d2 t d1 t d1 t d2 50% out-a for primary control for secondary control out-b out-c out-d out-e t d3 t d3 out-f 4. maximum/minimum phase shift is defined as; d = 2 100 (%) t 2 t 1 t 2 t 1 out-a out-d t 2 t 1 out-b out-c
ha16163t rej03f0001-0600 rev.6.00 jul 01, 2008 page 7 of 29 electrical characteristics (cont.) (ta = 25c, vcc = 12 v, rt = 33 k , rdelay = 51 k , unless otherwise specified.) item symbol min typ max unit test conditions pulse-by-pulse current limit threshold v cs-pp 0.36 0.40 0.44 v one-shot ocp threshold v cs-sd 0.54 0.60 0.66 v delay to out pins * 1 tpd-cs ? 40 80 ns cs = 0v to 0.47v over current protection timer latch integration time t tl 44 63 82 s cs = 0.47v step function, ss = 0.022 f high voltage v oh-out 4.3 4.8 ? v iout = ?5ma low voltage v ol-out ? 0.1 0.4 v iout = 5ma rise time tr ? 5 15 ns c out = 33pf fall time tf ? 5 15 ns c out = 33pf output timing offset * 2 t d4 ? 3 * 3 ? ns notes: 1. tpd-cs is defined as; 0.47v 0 50% 50% tpd-cs cs out-c/d 2. t d4 is defined as; 50% 50% t d4 out-d out-e 50% 50% t d4 out-c out-f 3. reference values for design. not 100% tested in production.
ha16163t rej03f0001-0600 rev.6.00 jul 01, 2008 page 8 of 29 timing diagram note: all voltage, current, time shown in the diagram is typical value. full bridge and secondary control t d2 t d2 t d3 t d3 ramp+0.4v (internal signal) comp/3(internal signal) 0.4v t d1 ramp comp out-a out-b out-c out-d out-e out-f t d1 external power stage drive ma mc out-a out-c drive drive mb md out-b ramp vin out-d out-e drive me mf drive drive out-f
ha16163t rej03f0001-0600 rev.6.00 jul 01, 2008 page 9 of 29 start-up and shutdown 9.8v 5v 0v 0v 4.0v 32 counts 32 counts low high low high 7.9v off on on vcc remote vref ss discharge (internal signal) vref good (internal signal) res (internal signal) soft-start block comp ramp ss comparator from error amp vref 4.0v clamp current information iss 10 a for phase modulation ss in discharge ? + 0.4v 20k 10k css
ha16163t rej03f0001-0600 rev.6.00 jul 01, 2008 page 10 of 29 timer latch and one shot ocp 3.78v 0.6v 3.9v 3.9v 0.4v out enable out disable 0.4v 4v 0.4v cs ss lockout (internal signal) seq. (internal signal) ocp block ? + res for phase modulation pulse by pulse ss in : voltage detector input of ss pin. seq. : timer latch function is not activated when seq. signal is low. short det. : discharge : gate control for ss capasitor reset. limit in : one shot ocp input. lockout : lock-out signal for out-a to f. vref good : system reset signal. vrefgood is high when either vref<4.6v or remote off mode. once one shot comparator detect short current in the power supply, short det. is high until ss voltage reaches down to 0.4v. 4v 87 a 10 a 0.4v ? + one shot 0.6v ss cs fault logic ? + r s q ss in 0.4v ? + 3.78v ? + 3.9v s r q s r q r s q discharge limit in all flip-flop are initialized by vref good in turn on period. vref good lockou t short det. seq.
ha16163t rej03f0001-0600 rev.6.00 jul 01, 2008 page 11 of 29 functional description note: all voltage, current, time shown in the diagram is typical value unless otherwise noted. uvlo uvlo (under voltage lockout operation) is a function that halts operation of the ic in the event of a low ic power supply voltage. when ic operation is halted, the 5 v internal voltage generation circuit (vref) halts, and therefore operation of circuitry using vref as the operating power supply halts . circuit blocks other than uvlo use vref as their operating power supply. therefore, the power supply current of the ic becomes equal to th e current dissipated by the uvlo circuit. the following graphs show the relationship between the vcc input current and vcc input voltage, and between vref and the vcc input voltage. icc vcc vcc icc 5v is 0 7.9v 9.8v 20v 8.5v 12v 0 7.9v 9.8v 20v vref figure 1 remote ic outputs (out-a through out-f) can be halted by means of the remote pin. in this case, the ic output logic level is low. in the remote off state, vref output is not halted, and ther efore the current dissipation of the ic does not decrease to the start-up level. also, control by means of the remote pin is not possible when the ic has been halted by uvlo. the soft start capacitance is discharged in the remote off stat e. therefore, operation begins from soft start mode when the next remote on operation is performed. the relationship between the remote pin and the operating mode of the ic is shown in the following figure. remote on off 1.333v 0v 1.417v 5v ic operating mode figure 2
ha16163t rej03f0001-0600 rev.6.00 jul 01, 2008 page 12 of 29 the remote on and off threshold voltages are provided with hysteresis of 84 mv (typ). remote control can be performed by means of analog input as shown in the diag ram below as well as by means of logic control. the following diagram shows an example in which the power supply set input voltage is sensed by means of the remote pin, and the power supply set start-up voltage is set to 34 v, and the shutdown voltage to 32 v. gnd ha16163 10k 10k 220k r2 r1 5v(vref) vin(on) = von(remote) (r1+r2)/r2 = 1.417v 24 = 34.008v vin(off) = voff(remote) (r1+r2)/r2 = 1.333v 24 = 31.992v remote control circuit (logic input) vin sense circuit (analog input) 100p remote power stage full-bridge control vin figure 3 start-up counter when the vref good signal (internal signal) goes to the logic low leve l, the ha16163 starts oper ating as a controller. the vref good signal is created from the re mote comparator and vrefgood circ uit output via a 32-clock start- up counter. + 5v generator start-up counter 32 clock on: 1.417v off: 1.333v remote vcc uvl l uvlo h l h vref good vref vref good from oscillator circuit bias figure 4 therefore, the start of ic operation is a 32-count later than uvlo release or the remote on trigger. when the oscillator frequency is set to 1 mhz, this represents a delay of 32 s. this delay enables operation to be halted until vref (5 v) stabilizes when uvlo is released. note that the start-up counter operates wh en vref rises or when a remote on operation is performed, but does not operate when vref falls or when a remote off operation is performed (there is no logic delay due to the start-up counter). 9.8v 7.9v 4.4v 4.6v 32 counts start of operation operation halted vcc vref vref good (internal signal) res (internal signal) figure 5
ha16163t rej03f0001-0600 rev.6.00 jul 01, 2008 page 13 of 29 oscillator the oscillation frequency of the oscillator is set by means of a resistance connected between the rt pin and gnd. the following graph shows the relationship between the external resistance and the oscillation frequency. the typical value of the oscillation frequency is given by the following equation. fosc = [hz] 1 25 [pf] rt [ ] + 150 [ns] ha16163 rt sync (2.7 v) rt gnd fosc vs. rt 10 100 1000 10000 10 100 1000 rt (k ) fosc (khz) figure 6 place the resistor for connection to the rt pin as close to the pin as is possible. please design the pattern so that the level of cross-talk from other signals is minimized. synchronized operation parallel synchronized operation is possible by connecting the sync pins of ha16163s. in this case, up to four slave ics can be connected to one master ic. a value of at least twice the master rt value should be set for the slave ic rt values. rt rt sync sync rt 2*rt (2.7v) (2.7v) gnd gnd ha16163 ha16163 rt sync 2*rt max. 4 slaves (2.7v) gnd master slave slave ha16163 figure 7 parallel synchronized operation
ha16163t rej03f0001-0600 rev.6.00 jul 01, 2008 page 14 of 29 external synchronized operation is possible by supplying a synchronization signal to the sync pins of ha16163s. in this case, a frequency not exceeding 1/2 that of the master clock should be set for the ha16163s. a maximum master clock frequency of 4 mhz should be used. see the figure below for the input waveform conditions. rt sync rt (2.7v) master clock gnd ttl or cmos ha16163 rt sync rt (2.7v) gnd master slave slave ha16163 figure 8 external synchronized operation t cycle t ih-sync t il-sync t il-min t i-min item input range t cycle 250ns min. t i-min 50ns min. t il-min 100ns min. v ih-sync 3.2v to vref v il-sync 0v to 2.5v figure 9 sync pin input conditions
ha16163t rej03f0001-0600 rev.6.00 jul 01, 2008 page 15 of 29 synchronous phase shift full-bridge control the ha16163 is provided with full-bridge control outputs out-a through out-d, and secondary-side synchronous rectification control outputs out-e and out-f. zvs (zero voltage switching) can be performed by adjusting timing delays t d1 and t d2 between the out-a through out-d outputs by mean s of an external resistance. out-e and out- f have an output timing suitable for secondary-side full-wave r ectification, and so can be us ed in either current doubler or center tap applications. the following figure shows full-bridge zvs + current doubler operation using an ideal model. t d1 t d3 t d2 vin 0 ?vin 0 vin/n ?vin/n 1 t0 subinterval: time: t5 t4 t3 t2 t1 2345 res pulse (internal signal) sa sb sc sd se sf transformer primary both-side voltage transformer secondary both-side voltage synchronous rectification control switch (on when high) full-bridge control switch (on when high) figure 10 ? subinterval: 1 in interval 1, sa and sd are turned on, and vin is generated on the transformer primary side. on the transformer secondary side, a value proportional to the winding ratio is generated, and the primary-side power is transmitted to the load side. at this time, secondary-side sw itch se is off and sf is on. sc sd se sf v12 vout sa lr l1 l2 sb cr1 cr2 v11 vin subinterval: 1
ha16163t rej03f0001-0600 rev.6.00 jul 01, 2008 page 16 of 29 ? subinterval: 2 as sd is turned off at point t1, the primary-side current flows into resonant capacitance cr2. at this time cr2 is charged, and therefore the potential of v12 rises. consid ering that the exciting current and the l1 and l2 ripple currents are considerable smaller than io, the following is an approximate equation for the slope of v12. = [v/s] ????? (1) dv12 dt 0.5 io n ? 1 cr2 here, n is the ratio of the primary coil to the sec ondary coil (n = n1/n2), and io is the output current. as se and sf are on, the transformer s econdary side is in the shorted state, and the value of the current flowing up to that time is retained. sc sd se sf v12 vout sa lr l1 l2 sb cr1 cr2 v11 vin subinterval: 2 ? subinterval: 3 sc is turned on at point t2. zvs operati on can be attained by setting the sd off (t2) sc on (t3) delay to the optimal value. this delay time can be expressed by equation (2). td2 = [s] ????? (2) n 0.5 io ? cr2 ? vin after sc is turned on, the transformer primary side is in the shorted state, and therefore the current value immediately after sc was turned on is retained. sc sd se sf v12 vout sa lr l1 l2 sb cr1 cr2 v11 vin subinterval: 3
ha16163t rej03f0001-0600 rev.6.00 jul 01, 2008 page 17 of 29 ? subinterval: 4 as sa is turned off at point t3, the primary-side current discharges resonant capacitance cr1, and the potential of v11 falls. a negative potential is applied to resonant inductor lr, and a flux reset starts. at this time, since the series resonance circuit is composed of cr1 and lr, the v11 waveform changes to a sine wave. the resonance frequency is given by equation (3). fr = [hz] ????? (3) 1 2 (cr1 ? lr) sc sd se sf v12 vout sa lr l1 l2 sb cr1 cr2 v11 vin subinterval: 4 ? subinterval: 5 when synchronous switch sf is turned off at point t4, the cu rrent flowing in sf up to that time continues to flow through the sf body diode. sf turn-off must be performed before completion of the resonant inductor lr flux reset. if sf is not off on completion of the lr flux reset, pow er transmission will be perf ormed with the transformer secondary-side shorted, and therefore an excessive current will flow in the tr ansformer primary and secondary sides, and parts may be damaged. also, if the sf body diode is on for a long period, loss will be high. therefore, opti mal timing should be set by means of the ha16163's delay adjustment pin, delay-3. lr reset time tr is given by equation (4) when the re sonance voltage peak value is within the input voltage. treset(lr)| vpp vin = = 0.5 (cr1 ? lr) [s] ????? (4) 1 4 1 fr ? here, vpp is the resonance voltage peak value. vpp = (lr/cr1) [v] ????? (5) io 2 1 n ?? sc sd se sf v12 vout sa lr l1 l2 sb cr1 cr2 v11 vin subinterval: 5
ha16163t rej03f0001-0600 rev.6.00 jul 01, 2008 page 18 of 29 ? time: t5 sb is turned on at point t5. the sb switching loss can be minimized by turning on sb when the sb both-side voltages are at a minimum (when the resonance voltage is at a peak). the sb turn-on timing can be set with td1 of the ha16163. the time when the resonance voltage is at a peak is given by equation (4). from t5 onward, operation is on the same principle as in subinterval 1 through subinterval 5. sc sd se sf v12 vout sa lr l1 l2 sb cr1 cr2 v11 vin time: t5
ha16163t rej03f0001-0600 rev.6.00 jul 01, 2008 page 19 of 29 delay setting inter-output delays (td1, td2, td3) are set by means of a resistance connected between the delay-1 (-2, -3) pin and gnd. the following graph shows the relationship between the external resistance and delay. the typical value of the delay set time is given by the following equation. td = 0.5 [pf] rd [ ] + 8 [ns] [s] when the rd value is small, the set time will be larger than the above calculated value due to the effect of internal delay, etc., and therefore a constant setting should be made with reference to the following graph. delay-1 (delay-2) (delay-3) rd (2.0v) gnd ha16163 1.00e+03 1.00e+00 1 1000 100 10 1.00e+01 1.00e+02 td vs. rd rd (k ) td (ns) figure 11 place the resistor for connection to the dela y-1,2,3 pin as close to the pin as is possible. please design the pattern so that the level of cross-talk from other signals is minimized. delay-3 (td3) there is a condition that secondary-side control output out- e and out-f delay td3 is 0 s (typical) in order to prevent shorting of the transformer secondary side. the relationship between td3 and the ic operating state is shown in the following table. mode definition operation of out-e, out-f note light load comp < 1.65v td3 = 0 1 pulse by pulse ocl cs 0.4v td3 = 0 2 one shot ocl cs 0.6v fixed low (operation halted) notes: 1. light-load detection is performed by means of t he error amplifier output vo ltage. light-load detection characteristics are as shown in the following diagram. td3 set value 0 comp voltage 1.46v 1.55v td3 light load detector characteristics ? + fb comp ramp vref comparator error amp. light load detector 500 1.25v ? + ? + 0.4v 20k 10k 2. td3 of the next out-e or out-f after the pulse-by-pulse current limiter (pbp ocl) operates is 0 s (typical). when out-c and out-d are subsequently inverted by the phase shift comparator, not the pbp ocl, td3 is restored to the value set by means of the delay-3 pin.
ha16163t rej03f0001-0600 rev.6.00 jul 01, 2008 page 20 of 29 application note: all voltage, current, time shown in the diagram are typical value. sample application circuits are given here. confirmatory experiments should be carried out when applying these examples to products. slope compensation in order to improve the unstable operation characteristic of curr ent mode, voltage slopes in a current sense signal can be superimposed. the following is a possible slope compensation method. ramp comparator ? + 0.4v compensated signal 5v(vref) res ha16163 r s q out-b out-c out-a out-d current sense signal figure 12 driving a pulse transformer out-a through out-f of this ic are cmos outputs that us e vref as their power supply. when directly driving a pulse transformer, the vref voltage fluc tuates according to the exciting current. as vref fluctuation may make internal circuit operation unstable, direct drive of a pulse transformer should be avoided. ? case 1 (ng) the figure below shows a case where a pulse transformer is driven directly. vref voltage fluctuation occurs due to the exciting current. out-e vref value fluctuates due to this exiting current ha16163 vref internal circuitry cref case 1 (ng)
ha16163t rej03f0001-0600 rev.6.00 jul 01, 2008 page 21 of 29 ? case 2 the figure below shows an example in which a current amplifier is added by means of transistors. a reverse current due to the exciting current is prevented by a blocking diode, and therefore capacitance cb is charged. in this way, fluctuation of the cref potential is suppressed and stable operation can be achieved. as well as a buffer implemented by means of a transistor, standard logic ic or buffer ic connection is also possible. the buffer circuit power supply method should be implemented in the same way. out-e ha16163 vref internal circuitry cref cb blocking diode case 2 ? case 3 the figure below shows an example of a drive power supply method using emitter following. for the same reason as described above, fluctuation of the cref potentia l is suppressed and stable operation can be achieved. out-e ha16163 vref internal circuitry cref cb vcc case 3 supplying power from an external power supply it is also possible to use an external source as the po wer supply for the ha16163t as shown in figure 13. the vref good circuit controls whether the ic is operating or stopped. the threshold voltage of the vrefgood circuit is 4.6 v (typ.) on the rising edge and 4.4 v on the falling e dge. since the ic?s characteristics vary with the value of the external voltage, this voltage must be provided by a high-precision 5-v source. vref vcc ha16163t vext 5v 2% figure 13
ha16163t rej03f0001-0600 rev.6.00 jul 01, 2008 page 22 of 29 characteristic curves uvl voltage vs. ambient temperature characteristics 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 ?40 ?25 0 25 50 75 100 125 vh (v) ta ( c) standby current vs. ambient temperature characteristics 0 20 40 60 80 100 120 140 160 ?40 ?25 0 25 50 75 100 125 is ( a) ta ( c) vcc = 8.5v vh vl
ha16163t rej03f0001-0600 rev.6.00 jul 01, 2008 page 23 of 29 operating current vs. ambient temperature characteristics 0 2 4 6 8 10 12 ?40 ?25 0 25 50 75 100 125 icc (ma) ta ( c) vref output voltage vs. ambient temperature characteristics 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 ?40 ?25 0 25 50 75 100 125 vref (v) ta ( c) no load on vref pin
ha16163t rej03f0001-0600 rev.6.00 jul 01, 2008 page 24 of 29 remote-on voltage vs. ambient temperature characteristics 1.34 1.36 1.38 1.40 1.42 1.44 1.46 1.48 ?40 ?25 0 25 50 75 100 125 v on (v) ta ( c) remote-off voltage vs. ambient temperature characteristics 1.26 1.28 1.30 1.32 1.34 1.36 1.38 1.40 ?40 ?25 0 25 50 75 100 125 v off (v) ta ( c)
ha16163t rej03f0001-0600 rev.6.00 jul 01, 2008 page 25 of 29 error amplifier feedback voltage vs. ambient temperature characteristics 1.20 1.22 1.24 1.26 1.28 1.30 ?40 ?25 0 25 50 75 100 125 v fb (v) ta ( c) fb and comp are shorted error amplifier source current vs. ambient temperature characteristics ?600 ?500 ?400 ?300 ?200 ?100 0 ?40 ?25 0 25 50 75 100 125 i source ( m a) ta ( c) fb = 0.75v, comp = 2v
ha16163t rej03f0001-0600 rev.6.00 jul 01, 2008 page 26 of 29 error amplifier sink current vs. ambient temperature characteristics 0 2 4 6 8 10 12 16 20 14 18 ?40 ?25 0 25 50 75 100 125 i sink (ma) ?15 ?14 ?13 ?12 ?11 ?10 ?9 ?7 ?5 ?8 ?6 iss ( a) ta ( c) soft-start pin current vs. ambient temperature characteristics ?40 ?25 0 25 50 75 100 125 ta ( c) fb = 1.75v, comp = 2v ss = 1v
ha16163t rej03f0001-0600 rev.6.00 jul 01, 2008 page 27 of 29 switching frequency vs. ambient temperature characteristics 380 400 420 440 460 480 500 540 580 520 560 ?40 ?25 0 25 50 75 100 125 fsw (khz) 15 20 25 30 40 50 35 45 td1 (ns) ta ( c) td1 delay vs. ambient temperature characteristics ?40 ?25 0 25 50 75 100 125 ta ( c)
ha16163t rej03f0001-0600 rev.6.00 jul 01, 2008 page 28 of 29 current sense delay time vs. ambient temperature characteristics 0 10 20 30 40 50 60 70 ?40 ?25 0 25 50 75 100 125 tpd (ns) ta ( c) overcurrent protection delay time vs. ambient temperature characteristics 0 20 40 60 80 100 ?40 ?25 0 25 50 75 100 125 tpd-cs (ns) ta ( c)
ha16163t rej03f0001-0600 rev.6.00 jul 01, 2008 page 29 of 29 package dimensions note) 1. dimensions" * 1 (nom)"and" * 2" do not include mold flash. 2. dimension" * 3"does not include trim offset. index mark e 1 y xm p * 3 * 2 * 1 f 10 20 11 a d e h z b terminal cross section ( ni/pd/au plating ) p c b 1 1 detail f a l l 0.65 0.10 0.65 6.20 6.60 0.20 0.15 a 1 6.80 max nom min dimension in millimeters symbol reference 1.10 0.6 0.5 0.4 4.40 0.10 0.07 0.03 0.25 0.20 0.15 0.10 6.40 8 0 0.13 1.0 6.50 l 1 z h e y x c b p a 2 e d b 1 c 1 e e l a p-tssop20-4.4x6.5-0.65 0.07g mass[typ.] ttp-20dav ptsp0020jb-a renesas code jeita package code previous code
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